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Hardware error correction encoding and decoding using FPGA

The latest coding techniques feature iteratively decodable codes such as turbo and low-density parity-check (LDPC) codes. As well as carrying out reserch, we need to ensure that our encoding and decoding algorithms can be used by industry. Accordingly, we are investigating high throughput and high speed FPGA encoder and decoder implementations of these codes and also our recently patented algorithms. Our implementation is able to correct all received bits in error in real-time and in the worst case, 20% of received bits maybe in error.

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Stopping sets and turbo codes

Turbo codes may be designed for large minimum Hamming distance by interleaver optimisation. However, under iterative decoding, the best error rate performance is not always achieved due the presence of stopping sets. For the erasure channel, stopping sets are clearly discernable and a fast algorithm to determine stopping sets is being developed. A preliminary study of this subject may be found here.

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